This invention relates to semiconductor devices, and more particularly to methods of making N-channel silicon gate MOS random access memories and the like.
In the manufacture of semiconductor devices such as MOS/LSI dynamic RAMs, the methods used are generally of the type described in U.S. Pat. No. 4,055,444, issued to G. R. Mohan Rao, assigned to Texas Instruments, referred to as the N-channel self-aligned gate process. In this process ion implant steps are used to adjust the threshold voltages of MOS field effect transistors to two or more levels. The transistors in the cell array, for example, need to have different threshold voltages compared to transistors in the input/output buffers in the peripheral circuitry on the chip, where perhaps two different thresholds are needed. Heretofore, two or more separate mask steps were used for these ion implant steps, one for each implant. This required a cleaning or stripping operation then another spin-on deposition of photoresist. Since the costs, cycle times, and yields are dependent upon the number of process steps, it is preferable to reduce the number of operations when possible.
It is the principal object of this invention to provide an improved method of making semiconductor memory devices or the like, yet still using basically the standard high volume N-channel MOS process. Another object is to provide a semiconductor device which is made by the standard N-channel self-aligned silicon gate manufacturing process but with a reduced number of process steps.